1. Field of the Invention
Embodiments of the present disclosure are directed to non-volatile memory technology.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
One example of a flash memory system uses the NAND structure, which includes arranging multiple transistors in series between two select gates. The transistors in series and the select gates are referred to as a NAND string. FIG. 1 is a top view showing one NAND string 30. FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 10, 12, 14 and 16 in series between a first select gate 12 and a second select gate 22. The drain select gate 12 connects the NAND string to bit line 26. The source gate 22 connects the NAND string to source line 28. Select gate 12 is controlled by applying appropriate voltages to control gate 20CG via selection line SGD. Select gate 22 is controlled by applying the appropriate voltages to control gate 22CG via selection line SGS. Each of the transistors 10, 12, 14 and 16 includes a control gate and a floating gate, forming the gate elements of a memory cell. For example, transistor 10 includes control gate 10CG and floating gate 10FG. Transistor 12 includes control gate 12CG and a floating gate 12FG. Transistor 14 includes control gate 14CG and floating gate 14FG. Transistor 16 includes a control gate 16CG and a floating gate 16FG. Control gate 10CG is connected to word line WL3, control gate 12CG is connected to word line WL2, control gate 14CG is connected to word line WL1, and control gate 16CG is connected to word line WL0. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner.
Note that although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, etc. The discussion herein is not limited to any particular number of memory cells in a NAND string. Relevant examples of NAND-type flash memories and their operation are provided in the following U.S. patents/patent applications, all of which are incorporated herein by reference in their entirety: U.S. Pat. No. 5,570,315; U.S. Pat. No. 5,774,397; U.S. Pat. No. 6,046,935; U.S. Pat. No. 5,386,422; U.S. Pat. No. 6,456,528; and U.S. patent application Ser. No. 09/893,277 (Publication No. U.S. 2003/0002348). Other types of non-volatile memory in addition to NAND flash memory can also be used in accordance with embodiments.
A typical architecture for a flash memory system using a NAND structure will include several NAND strings. For example, FIG. 3 shows three NAND strings 40, 42 and 44 of a memory array having many more NAND strings. Each of the NAND strings of FIG. 3 includes two select transistors or gates and four memory cells. NAND string 40 includes select transistors 50 and 60, and memory cells 52, 54, 56 and 58. NAND string 42 includes select transistors 70 and 80, and memory cells 72, 74, 76 and 78. Each string is connected to the source line by a source select gate 60, 80, etc. A selection line SGS is used to control the source side select gates. The various NAND strings are connected to respective bit lines by drain select gates 50, 70, etc., which are controlled by select line SGD. In other embodiments, the select lines do not necessarily need to be in common. Word line WL3 is connected to the control gates for memory cell 52 and memory cell 72. Word line WL2 is connected to the control gates for memory cell 54 and memory cell 74. Word line WL1 is connected to the control gates for memory cell 56 and memory cell 76. Word line WL0 is connected to the control gates for memory cell 58 and memory cell 78. A bit line and respective NAND string comprise a column of the array of memory cells. The word lines comprise the rows of the array. Each word line connects the control gates of each memory cell in the row. For example, word line WL2 is connected to the control gates for memory cells 54, 74 and 94. In many implementations, the word lines form the control gate of each memory cell in the row.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. The floating gate charge and threshold voltage of the cell can be indicative of a particular state corresponding to stored data (analog or digital). More information about programming can be found in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, incorporated herein by reference in its entirety.
To apply the program voltage to the control gate of the cell being programmed, that program voltage is applied on the appropriate word line. As discussed above, that word line is also connected to one cell in each of the other NAND strings that utilize the same word line. For example, when programming cell 54 of FIG. 3, the program voltage will also be applied to the control gate of cell 74 because both cells share the same word line WL2. A problem arises when it's desired to program one cell on a word line without programming other cells connected to the same word line. Because the program voltage is applied to all cells connected to a word line, an unselected cell connected to the selected word line receiving the program voltage, especially a cell adjacent to the cell selected for programming, may be inadvertently programmed. The unintentional programming of the unselected cell on the selected word line is referred to as “program disturb.”
Several techniques can be employed to prevent program disturb. In one method known as “self boosting,” the channel areas of the unselected NAND strings are electrically isolated and a pass voltage (e.g. 10V) is applied to the unselected word lines during programming. The unselected word lines couple to the channel areas of the unselected NAND strings, causing a voltage (e.g. 8V) to be impressed in the channel and source/drain regions of the unselected NAND strings, thereby reducing program disturb. Self boosting causes a voltage boost to exist in the channel which lowers the voltage across the tunnel oxide and hence reduces program disturb.
FIGS. 4 and 5 depict NAND strings that are being programmed and inhibited using a self-boosting method, respectively. FIG. 4 depicts a NAND string being programmed. The NAND string of FIG. 4 includes eight memory cells 102, 104, 106, 108, 110, 112, 114, 116 connected in series between drain select gate 120 and source select gate 122. Drain select gate 120 connects the string to a particular bit line BLP via contact 124 and source select gate 122 connects the string to a common source line SL via contact 126. Between each of the floating gate stacks are source/drain regions 130. FIG. 5 depicts a NAND string being inhibited from programming. The NAND string includes eight memory cells 152, 154, 156, 158, 160, 162, 164, 166 connected in series between drain select gate 170 and source select gate 172. Drain select gate 170 connects the string to a different bit line BLI via contact 174 and source select gate 172 connects the string to the common source line SL via contact 176. Between each of the floating gate stacks are source/drain regions 180.
Each memory cell of FIGS. 4 and 5 includes a floating gate (FG) and a control gate (CG). The memory cells can be formed in a p-well, which itself may be formed within an n-well on a p-type substrate e.g., silicon. The p-well may contain a so called channel implantation, usually a p-type implantation that determines or helps to determine the threshold voltage and other characteristics of the memory cells. The source/drain regions 130 and 180 are n+ doped regions formed in the p-well in one embodiment.
The memory cells of both NAND strings are connected to a common set of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7. A selected word line WL4, for example, receives a program voltage Vpgm. The program voltage typically comprises a series of voltage pulses (e.g., 12V-24V) that increase in magnitude between each pulse. A boosting voltage Vpass is applied to each other word line. The source select gates 122, 172 are in an isolation mode and a low voltage is applied to the source line SL. The low voltage can be about 0V or a slightly higher voltage to provide better isolation characteristics at the source select gate. The drain select gates are turned on by application Of Vsgd which can be about 1.5-3.5V.
The NAND string in FIG. 4 that is enabled for programming receives 0V at its bit line BLP. With the drain select gate 120 turned on, the 0V is transferred to the channel region of the string. Channel region 140 below the selected memory cell 110 is at or close to 0V, along with the channels of each other cell of the string. Because of the voltage differential between the channel and the floating gate of memory cell 110, electrons tunnel through the gate oxide (also commonly referred to as tunnel oxide) into the floating gate by Fowler-Nordheim tunneling.
The NAND string of FIG. 5 receives the power supply voltage Vdd via its corresponding bit line BLI in order to inhibit the programming of memory cell 160, which receives Vpgm on WL4. When Vdd is applied, the drain select transistor 170 will initially be in a conducting state. Therefore, the channel area under the NAND string will partly be charged to a higher potential (higher than 0V and typically equal or almost equal to Vdd). This charging is commonly referred to as pre-charging. Typically, a larger voltage Vsg (e.g., 4.0V-4.5V) is applied to the drain select transistor during pre-charging. The pre-charging will stop automatically when the channel potential has reached Vdd or a lower potential given by Vsg−VT, where VT is equal to the threshold voltage of the drain select gate 170. In general, during pre-charging, Vsg is chosen in such a way that Vsg−VT>Vdd so that the channel area under the NAND string can be pre-charged to Vdd. After the channel has reached that potential, the select gate transistor is non-conducting or made non-conducting by lowering Vsg to a value of about Vsgd (e.g. 1.5V3.5V), depending on the level of Vdd and the select gate threshold voltage. Subsequently, the voltages Vpass and Vpgm are ramped up from 0V to their respective final values (not necessarily at the same time), and because the drain side select gate transistor 170 is in a non-conducting state, the channel potential will start to rise because of capacitive coupling between the word lines and the channel area (typically around 50%). This phenomenon is called self boosting. The channel area under the NAND string of FIG. 5 is boosted, more or less uniformly, to a boosted voltage level. Region 190 depicts the boosted channel region of the NAND string. Because the voltage differential between the floating gate of memory cell 160 and the underlying channel region 192 has been reduced, programming is inhibited. Note that FIG. 5 shows region 190, which includes a channel area at the surface of the substrate and a depletion layer (an area with increased electrical field due to the channel that is boosted to a high voltage) under the boosted channel area. The channel area exists under each of the floating gate/control gate stacks and between the source/drain regions 180. More information about programming NAND flash memory, including self boosting techniques, can be found in U.S. Pat. No. 6,859,397, “Source Side Self Boosting Technique for Non-Volatile Memory,” Lutze et al., incorporated herein by reference in its entirety.
Referring to FIG. 3, a NAND string is typically (but not always) programmed in sequence from the source side to the drain side, for example, from memory cell 58 to memory cell 52. When the programming process is ready to program the last (or near the last) memory cell of the NAND string, if all or most of the previously programmed cells on the string being inhibited (e.g. string 42) were programmed, there is negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the boosting potential may not get high enough and there still may be program disturb on the last few word lines. For example, when programming cell 52, if cells 74, 76 and 78 were programmed, then each has a negative charge at its floating gate which will limit the boosting level of the self boosting process and possibly allow program disturb on cell 72.
Another self boosting technique is Local Self Boosting (“LSB”) which attempts to isolate the channel of the cell being inhibited. The word lines neighboring the selected word line are typically at 0V and the remaining non-selected word lines are at Vpass. Yet another boosting method, called EASB, attempts to isolate the channel of previously programmed cells from the channel of the memory cell being inhibited. In the EASB method, the channel area of the selected NAND string is divided into two areas: an area at the source side of the selected word line that can contain a number of programmed (or erased cells) memory cells and an area at the drain side of the selected word line in which the cells are still in the erased state, or at least not yet in the final programmed state. The two areas are separated by a word line that is biased to a low isolation voltage, typically 0V. Because of this separation, the two areas can be boosted to different potentials. In almost all cases, the area at the drain side of the selected word line will be boosted to a higher potential than the area at the source side. Another boosting scheme, known as Revised Erased Area Self Boosting (REASB) is similar to EASB, except that between the word line receiving the isolation voltage and the selected word line is a word line receiving an intermediate voltage (between Vpass and the isolation voltage).
While LSB and EASB provide an improvement over self boosting, they also present a problem that depends on whether the adjacent source side memory cell is programmed or erased. If the adjacent source side cell is programmed, then there is a negative charge on its floating gate. With 0V applied to its control gate, there is a highly reverse biased junction under the negatively charged gate which can cause Gate Induced Drain Leakage (GIDL), also referred to as band-to-band tunneling.
GIDL can also occur at the select gates, especially at the source side select gate. GIDL causes the generation of electrons at the source select gate when the channel under the NAND string is inhibited from programming (boosted to a high voltage). Subsequently, the generated electrons are accelerated in the strong lateral electric field towards the floating gate of the memory cell next to the source select gate. Some of the electrons can gain sufficient energy to be injected into the tunnel oxide under the floating gate or in the floating gate itself and thus, modify the threshold voltage of the corresponding memory cell. FIG. 6 shows a portion of the NAND string of FIG. 5, zooming-in on the drain of the source select gate and a portion of the channel for memory cell 152. Due to boosting of the NAND string during a program inhibit operation (for example when other NAND strings are being programmed), a high voltage is present in the channel area of the boosted NAND string. This high voltage is also present at the junction area between source select gate 172, which is typically biased at 0V, and memory cell 152 next to source select gate 172. This bias condition may cause the creation of electron-hole pairs, also known as GIDL. The holes will go to the p-well area 150. The electrons will move to the boosted channel area. In general, there is a lateral electric field present in the junction area between the source select gate and the memory cell next to the source side select gate because part of that junction (drain/source) is depleted due to the large voltage difference between channel area under the memory cells and the channel area under the select gate. The electrons can be accelerated in the electric field and may gain enough energy to be injected in the tunnel oxide of the memory cell next to the source side select gate or may even reach the floating gate of that memory cell. In both cases, the threshold voltage of the corresponding memory cell will change due to the presence of the injected electrons, thereby, risking an error when reading the memory cell next to the source select gate. To reduce the effects of GIDL, the boosting voltage Vpass can be lowered to reduce the amount of channel boosting during the inhibit operation. However, this may result in program disturb due to insufficient boosting.